Ip and Subsystem Validation Engineering Manager

Intel Intel · Semiconductors · Bangalore, India

This role is for an IP and Subsystem Validation Engineering Manager at Intel, focusing on ensuring the reliability and functionality of cutting-edge IP designs. Responsibilities include developing verification plans, executing simulations, debugging issues, and collaborating with cross-functional teams. Requires a strong background in RTL design, verification methodologies, and leadership experience.

What you'd actually do

  1. Develop detailed IP verification plans and implement advanced test benches and environments to validate designs against specifications.
  2. Execute verification plans by running system simulation models to analyze functionality, power, and timing.
  3. Identify, replicate, root cause, and debug issues in the presilicon environment, ensuring that all failing tests are addressed and resolved.
  4. Collaborate closely with architects, RTL developers, and physical design teams to improve verification coverage and enable successful delivery of complex features.
  5. Document verification test plans, results, and methodologies; lead technical reviews with internal teams to ensure alignment and quality.

Skills

Required

  • RTL Design
  • Verilog
  • SystemVerilog
  • Design for Verification (DFV)
  • IP validation tools
  • test writing
  • test planning
  • simulation
  • debugging techniques
  • Formal Verification
  • Assertion-Based Verification
  • Coverage-Based Verification
  • problem-solving skills

Nice to have

  • collaborative, cross-functional teams
  • technical documentation
  • team presentations
  • Leadership experience
  • mentoring junior team members
  • industry trends, tools, and methodologies for IP design and verification

What the JD emphasized

  • 12+ years of relevant experience
  • 8+ years of experience
  • 6+ years of experience
  • RTL Design
  • SystemVerilog
  • Formal Verification
  • Assertion-Based Verification
  • Coverage-Based Verification