Ip Logic Design Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Develops logic design, RTL coding, and simulation for IP blocks, optimizing for power, performance, area, and timing. Supports SoC customers and ensures quality integration and verification of IP blocks for full chip designs. Requires expertise in microarchitecture, high-speed designs, timing convergence, low-power techniques, and protocols like PCIe and CXL.

What you'd actually do

  1. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  2. Participates in the definition of architecture and microarchitecture features of the block being designed.
  3. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
  4. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
  5. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

Skills

Required

  • Bachelor's degree in Electronics Engineering, Computer Engineering, or a related field
  • 9+ years of professional experience in hardware design (or 6+ with Master's, 4+ with PhD)
  • Microarchitecture expertise
  • RTL development expertise
  • Logic development expertise for high-speed designs (gigahertz range)
  • Timing convergence proficiency
  • Low-power design techniques knowledge
  • PCIe protocol understanding
  • CXL protocol understanding

Nice to have

  • Experience in conducting design reviews
  • Experience in validation processes for complex IP architectures
  • Effective communication skills
  • Ability to collaborate within cross-functional teams

What the JD emphasized

  • 9 or more years of professional experience in hardware design with a bachelor's degree, or 6 or more years of experience with a master's degree, or 4 or more years of experience with a PhD
  • Expertise in microarchitecture, RTL, and logic development for high-speed designs operating in gigahertz range frequencies
  • Proficiency in timing convergence of complex designs, including resolving timing closure issues
  • Advanced knowledge of low-power design techniques, such as power gating and clock domain crossing
  • Strong understanding of PCIe and CXL protocols and their integration into hardware