Ip Logic Design Engineer

Intel Intel · Semiconductors · Bangalore, India

Intel is seeking an IP Logic Design Engineer to develop logic designs for high-performance IPs integrated into SoC products for Client, Graphics, and Data Center markets. Responsibilities include RTL implementation, architecture specification, optimization, verification support, and post-silicon validation.

What you'd actually do

  1. Own and deliver logic design and RTL implementation for IP development, ensuring sign-off verification for functionality, reliability, and synthesis checks.
  2. Develop architecture and microarchitecture specifications for logic components, driving area, power, and performance optimizations.
  3. Apply advanced strategies and tools for RTL coding, simulation, and debug, ensuring designs meet power-performance-area (PPA) goals and timing integrity.
  4. Collaborate with verification teams to review and execute verification plans, resolve failing RTL tests, and implement corrective measures to ensure design feature correctness.
  5. Support SoC integration efforts, ensuring high-quality IP handoffs and seamless integration into full-chip designs.

Skills

Required

  • System Verilog
  • RTL coding
  • digital design techniques
  • clock domain crossing
  • microarchitecture debugging
  • simulation debugging
  • static timing analysis
  • low-power design strategies
  • clock gating
  • UPF methodologies
  • LINT
  • CDC
  • RDC
  • timing analysis
  • synthesis
  • regression
  • code coverage
  • analytical skills
  • pre-silicon design challenges
  • post-silicon design challenges

Nice to have

  • AMBA protocols (CHI, AXI, AHB, APB)
  • PCIe
  • CXL standards
  • architecture development
  • microarchitecture development for IP subsystems
  • physical design teams
  • mixed-signal designs
  • behavioral coding
  • behavioral simulations
  • PPA trade-offs
  • innovative design solutions
  • communication skills
  • collaboration across geographically distributed teams

What the JD emphasized

  • 6+ years of experience in logic design and RTL development
  • Expertise in System Verilog and RTL coding
  • demonstrated experience in clock domain crossing, debugging microarchitecture/simulation, and static timing analysis
  • Proficiency in low-power design strategies, including clock gating and UPF methodologies
  • Strong analytical skills and hands-on experience resolving pre-silicon and post-silicon design challenges