Ip/soc Verification With Power Management Engineer

AMD AMD · Semiconductors · Hyderabad, India · Engineering

This role is for an IP/SOC Verification Engineer with a focus on power management features for Server SOCs. Responsibilities include developing test plans, creating coverage models, building UVM testbenches, verifying power management interactions, debugging issues, and ensuring functional coverage closure. The role also involves participating in architecture reviews and supporting post-silicon validation.

What you'd actually do

  1. Develop comprehensive test plans for power management features across Server SOC
  2. Create coverage models for P-state, C-state, and power gating scenarios
  3. Build UVM testbenches with power-aware verification components
  4. Verify cross-IP power management interactions and dependencies
  5. Debug RTL/testbench issues and work with design teams for resolution

Skills

Required

  • UVM testbenches
  • power management features
  • Server SOC
  • RTL/testbench debugging
  • functional coverage closure

Nice to have

  • Python/Perl/TCL scripting
  • waveform debugging tools (Verdi, DVE, Simvision)
  • PCIe, CXL, DDR5, LPDDR5, ACPI
  • post-silicon validation and debug methodologies
  • problem-solving and analytical skills
  • communication and collaboration