Ip Validation Design Engineer

AMD AMD · Semiconductors · VANCOUVER, BC · Engineering

AMD is seeking an IP Validation Design Engineer to join their NBIO Team. The role involves planning, validating, and debugging hardware IP for AMD's SOC programs, including defining test plans, developing automation scripts, debugging issues across various phases (pre-silicon to production), and collaborating with cross-functional teams like DV and Emulation. Experience with digital logic design, ASIC debug, high-speed interfaces (PCIe/CXL), and scripting (Python/Ruby) is preferred.

What you'd actually do

  1. Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s.
  2. Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
  3. Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.
  4. Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.
  5. Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.

Skills

Required

  • Bachelor’s or master’s degree majoring in EE, CS or related field
  • Excellent written and verbal communication skills
  • Self-starter
  • Able to independently drive tasks to completion
  • Excel in a dynamic team working environment

Nice to have

  • Experience in digital logic design/verification/post-silicon validation
  • Extensive experience with ASIC debug techniques and methodologies
  • Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK
  • Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
  • Strong scripting skills (eg. Ruby, Python)
  • Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
  • In-depth knowledge of PC architectures/PCIe protocol
  • Leadership and mentoring skills

What the JD emphasized

  • Must have excellent written and verbal communication skills.
  • Must excel in a dynamic team working environment.
  • Must be a self-starter and be able to independently drive tasks to completion.