Ip Verification Engineer

AMD AMD · Semiconductors · Hyderabad, India · Engineering

This role focuses on planning, building, and executing the verification of new and existing features for AMD's graphics processor IP. The engineer will collaborate with architects and other engineers, build test plans, write directed and random verification tests, and debug test failures. The role requires proficiency in IP level ASIC verification, debugging firmware and RTL code, and experience with UVM testbenches, Verilog, System Verilog, C, and C++.

What you'd actually do

  1. Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  2. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  3. Estimate the time required to write the new feature tests and any required changes to the test environment
  4. Build the directed and random verification tests
  5. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

Skills

Required

  • IP level ASIC verification
  • debugging firmware and RTL code
  • UVM testbenches
  • Verilog
  • System Verilog
  • C
  • C++

Nice to have

  • Linux
  • Windows environments
  • Graphics pipeline knowledge
  • AXI, ACE Protocols
  • Ethernet, PCIe, USB
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • simulation profile, efficiency improvement, acceleration, HLS tools/process
  • C++ language, preferably on Linux with exposure to Windows platform
  • UVM concepts and SystemVerilog language
  • SystemC and TLM
  • Perl, Ruby, Makefile, shell
  • leadership or mentorship
  • video codec system or other multimedia solutions

What the JD emphasized

  • no bugs in the final design