Lead Ate Test Development Engineer - Lpu

NVIDIA NVIDIA · Semiconductors · Santa Clara, CA

NVIDIA is seeking a Lead ATE Test Development Engineer for their LPU team. This role involves defining, developing, and implementing ATE test programs for LPU products, working with overseas manufacturing teams to improve yields and reduce costs, and collaborating with cross-functional teams to debug failures and enhance reliability. The position requires a Bachelor's degree in Electrical/Computer Engineering, 12+ years of VLSI ATE testing experience, and proficiency with Advantest 93K ATE platform.

What you'd actually do

  1. Serve as the lead for defining, developing, implementing and supporting ATE test development. This includes, defining test programs, driving test hardware development, leading bring up of new silicon, characterization and enabling production release of our latest LPU product.
  2. Develop test methods and provide guidance on streamlining test program development to provide the best possible coverage on ATE to reduce DPPM downstream.
  3. Work closely with the SLT and system validation teams to understand how failures at the system level can be replicated on ATE to implement critical tests and/or test conditions on ATE
  4. Work collaboratively with the system architects, silicon design, and operations teams to understand the chip application in field and implement new test strategies on ATE to improve reliability and DPPM in the field.
  5. Actively participate with cross functional teams including Product Development Engineering, DFT, and IC design to efficiently debug product failures and implement optimal solutions.

Skills

Required

  • Bachelor Degree or higher in Electrical Engineering/Computer Engineering (or equivalent experience).
  • 12+ years of relevant experience in IC Design, application or ATE testing of VLSI.
  • Working knowledge and hands-on experience with Advantest 93K ATE platform (SmarTest 7 and 8) are essential
  • Critical thinking, good communication and collaboration skills
  • Excellent debugging and analytical skills
  • Understanding of DFT insertion techniques including SCAN, ATPG, MBIST and IOBIST.

Nice to have

  • Test Hardware design knowledge specifically for Signal and Power integrity
  • System level testing/validation exposure
  • Product engineering experience, such as yield analysis, vmin/fmax characterization, defect analysis
  • Linux operating systems, and programming languages such as Perl/Python and/or C/C++, Java
  • Industry experience with high power, high volume deployment of high quality and reliable SOCs via ATE test development

What the JD emphasized

  • essential
  • Critical thinking
  • Excellent debugging and analytical skills
  • high power, high volume deployment of high quality and reliable SOCs via ATE test development