Job Details:
Job Description:
Intel is seeking a Lead Design Verification Engineer for the Silicon Chassis team. In this technical leadership role, you will define end-to-end verification strategy and execution for multiple critical chassis and interconnect IP programs from planning through signoff. You will partner closely with architecture, design, software, and methodology teams to make early technical calls, unblock cross-team issues, and drive predictable high-quality delivery. This role requires deep DV expertise, strong protocol and memory subsystem knowledge, and enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.
Responsibilities
Define verification strategy, technical standards, and execution model for critical blocks and ensure delivery scales from IP through subsystem integration across multiple programs
Lead development of reusable environments, tools, and targeted testplans, including complex testbenches, checkers, VIPs, and behavioral models
Collaborate closely with architecture, design, software, and methodology teams from specification through bringup; contribute across role boundaries when needed to unblock execution and maintain delivery quality
Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
Drive convergence of simulation, formal, and emulation-based verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
Mentor and develop senior and junior verification engineers; establish verification best practices and raise team-level execution quality
Qualifications:
Minimum Qualifications
BS/MS in Electrical Engineering, Computer Science, or related field, with 14+ years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification
Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA CHI, ACE, AXI, PCIe, UCIe, and CXL; strong foundation in memory management MMUs, cache coherency models and memory consistency implementation
Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features
Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow; track record of developing and delivering highly configurable and reusable verification collateral
Working familiarity with RTL, physical design constraints, and CAD tool flows; enough to read, review, and contribute outside core DV responsibilities
Demonstrated experience collaborating with formal verification and emulation teams to develop multi-engine verification strategies and drive closure across engines
Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule and establishing technical standards; able to adapt as tools, methodologies, and role definitions evolve
Preferred Qualifications
Hands-on experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining simulation, formal, and emulation for unified bug closure
Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
- ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.