Lead Dfx Silicon Design Engineer at AMD

What you'd actually do

Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology.

Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows

Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS.

Writing and maintain DFT documentation and specifications.

Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.

Skills

Required

DFT RTL design
DFT RTL integration
Synthesis
Equivalency checking
Timing analysis
Verification of DFx logic
DFT documentation and specifications
CAD software development
Scripting languages (TCL, c-shell, Perl)
Verilog
Waveform debugging tools
UNIX/Linux
C++ programming
EDA tools/methodology
JTAG/IEEE standards
Scan and ATPG
On-chip test pattern compression
At-speed testing using PLL
Memory BIST and repair
Logic BIST
Power-gating
On-chip debug logic
Testing of high speed SerDes IO
Analog design

Nice to have

ATE and digital IC manufacturing test

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **

THE ROLE:

AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.

THE PERSON:

As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

KEY RESPONSIBILITIES:

Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology.
Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows
Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS.
Writing and maintain DFT documentation and specifications.
Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design.
Performing scan insertion, ATPG verification and test pattern generation
Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis.

PREFERRED EXPERIENCE:

Experience in DFT design, integration, verification, ATPG and Silicon Debug experience.
Demonstrated technical leadership and works well with cross-functional teams.
Excellent communication and interpersonal skills
Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc.
Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
Experience in solving logic design or timing issues with integration, synthesis and PD teams.
Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming
Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis.
Knowledge of ATE and digital IC manufacturing test is a plus.
Strong problem-solving skills.
Team player with strong communication skills.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in electrical/Electronic Engineering with 12+Yrs of exp

#LI-SR4

_Benefits offered are described: _AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

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This posting is for an existing vacancy.