Lead Formal Verification Engineer

AMD AMD · Semiconductors · Austin, TX · Engineering

Lead Formal Verification Engineer at AMD, focusing on graphics IP design. Responsibilities include defining formal verification strategy, developing cutting-edge methodologies, building infrastructure, and leading research in emerging formal verification domains. Requires expertise in formal verification algorithms, system Verilog assertions, and formal verification tools, with a proven track record in processor design.

What you'd actually do

  1. Define long-term strategy for formal verification expansion and steer the technical roadmap
  2. Develop cutting-edge formal verification methodology to cover the whole graphics design, including both datapath and control logic. Scale formal verification to big and critical design for bug-free quality. Expand formal verification adoption to the whole IP development life cycle. Resolve challenging convergence issue through world class formal verification techniques like induction, reduction, abstraction, etc.
  3. Define and drive the best-in-class formal verification infrastructure to improve formal verification productivity. Enable more verification engineers to adopt this advanced verification technology without deep formal verification knowledge
  4. Lead the research group for emerging formal verification domains like security, safety, low power, architect level formal verification, etc. Explore the feasibility of formalizing ISA and memory model for GFXIP design
  5. Stay informed of latest trends and innovations in formal verification. Develop technical relationship with broader AMD Design community and peers. Drive cross-department innovation and collaboration inside AMD

Skills

Required

  • Formal verification algorithms
  • Formal verification engines
  • Formal verification use cases
  • System Verilog assertion development
  • Abstract model development
  • Formal verification tools (JasperGold, VC formal, Murphi, theorem prover)
  • Processor design
  • Computer architecture
  • Graphics pipeline
  • Formal verification infrastructure development
  • FPV
  • DPV
  • SEV

Nice to have

  • Leadership skills
  • Master or PhD degree in Computer Science/ Computer Engineering/ Electrical Engineering

What the JD emphasized

  • cutting-edge formal verification techniques
  • cutting-edge formal verification methodology
  • bug-free quality
  • world class formal verification techniques
  • best-in-class formal verification infrastructure
  • advanced verification technology
  • emerging formal verification domains
  • formalizing ISA
  • formal verification