In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Machine Learning Hardware Architect within the Co-design team, you will serve as a technical lead bridging model architecture innovation and next-generation hardware design. Operating at the highest levels of AI research and engineering, you will define the goal and architectural roadmap for our future machine learning serving and training capabilities. You will guide the integration of ML research such as massive-scale foundation models with advanced silicon architectures to create industry-leading, high-performance, and power-efficient accelerators.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Define and drive the technical roadmap and architecture for the hardware/software stack to ensure exceptional performance for ML models. Act as the technical liaison across research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
- Architect next-generation configurable simulation frameworks and performance models, setting the organizational standard for evaluating complex microarchitectural decisions. Drive high-stakes choices regarding Power, Performance, Area (PPA) and buildability for future chip and system architectures, expertly balancing long-term technological trends with strict product delivery timelines.
- Guide system-level performance analysis across highly distributed ML systems, innovating new methodologies to optimize and balance compute, memory bandwidth, and inter-chip network requirements. Their leadership will directly shape the future of high-performance AI infrastructure and hardware-software co-design.
- Manage cross-functional partnerships across hardware, compiler development and ML teams.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 12 years of experience in computer architecture, chip architecture, or hardware-software co-design.
- Experience architecting and developing software systems in C++ or Python for performance modeling, simulation, or system analysis.
Preferred qualifications:
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
- Experience as a lead architect managing multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.
- Experience in semiconductor technologies, industry trends, and the future trajectory of process, memory, interconnects, and packaging.
- Experience with deep learning frameworks (e.g., TensorFlow, PyTorch) and deep understanding of their underlying execution models.