Memory Subsystem Architect and Design Engineer

AMD AMD · Semiconductors · Santa Clara, CA · Engineering

This role focuses on the hardware architecture and design of memory subsystems for next-generation network hardware, particularly within an AI-driven roadmap. Responsibilities include leading architecture, bring-up, root cause analysis, debugging of memory issues (DDR5/DDR4), collaborating with IP vendors and board designers, and identifying hardware improvements. While the roadmap is AI-driven, the core function is hardware engineering, not AI/ML model development.

What you'd actually do

  1. Lead the architecture and bring up of hardware systems and products involving next-gen memory subsystems.
  2. Investigate, hand-on debug and resolve next-gen and legacy memory issues, including root cause analysis and corrective action.
  3. Identify opportunities for hardware improvements, second sourcing, and cost reductions.
  4. Maintain and update technical documentation, including design documents, user manuals, and technical notes.
  5. Collaborate with stakeholders, including product management, sales, and marketing, to understand customer requirements and market needs.

Skills

Required

  • Deep expertise in memory hardware
  • Hands-on experience across recent generations of DDR5 and DDR4 in both design and debug
  • Hardware engineering
  • Hardware troubleshooting
  • Hardware design principles
  • Hardware development tools
  • Hardware validation and test methodologies
  • Memory test equipment

Nice to have

  • Python
  • Altium
  • Cadence
  • SPICE
  • MS in Electrical or Computer Engineering