Memory Subsystem (shift Left) Lead

AMD AMD · Semiconductors · MARKHAM, Canada · Engineering

This role is for a senior technical leader in AMD's Memory Subsystem team, focusing on pre-silicon execution and SoC integration of DDR subsystems. The role involves defining features, architecture, and technical specifications, collaborating with cross-functional teams, and ensuring alignment across hardware, firmware, BIOS, and software for performance and power optimization. It also includes supporting design and post-silicon teams for issue resolution.

What you'd actually do

  1. Define product features and capabilities; contribute to architecture and micro-architecture requirements; help develop technical specifications for SoC and IP blocks; and provide technical guidance to execution teams
  2. Understand the SoC as a complete system, including hardware (silicon), firmware, BIOS, and software, and work to ensure alignment across these components to enable features while optimizing performance and power
  3. Work cross-functionally with IP and domain architects to identify and assess complex technical issues and risks, and collaborate on architectural approaches to meet product requirements
  4. Share knowledge and contribute to Platform & System Architecture discussions and documentation
  5. As a primary technical steward, support architecture analysis and technical solutions related to feature updates and change requests

Skills

Required

  • Systems and SoC architecture
  • CPU or GPU, memory subsystems, fabrics, CPU/GPU coherency, multimedia, I/O subsystems, clocks, resets, virtualization, or security
  • analyzing CPU-, GPU-, or system-level micro-architectural features to understand performance characteristics across workloads
  • power management microarchitecture, low-power design, and power optimization, including awareness of power impact at the architecture, logic design, and circuit levels
  • Clear, effective communication and collaboration skills, including the ability to work across disciplines and experience levels
  • Comfort collaborating with architects and engineering partners across teams and geographies, with an inclusive and respectful working style
  • Bachelor’s or master’s degree in computer engineering, Electrical Engineering, or equivalent practical experience

Nice to have

  • production firmware
  • BIOS
  • software
  • IP blocks
  • area and floorplan considerations
  • verification test plan reviews
  • timing targets
  • emulation plans
  • pre-silicon issue resolution
  • performance and power verification signoffs
  • post-silicon teams
  • debug and resolution of product performance, power, and functional issues

What the JD emphasized

  • DDR Subsystem Shift Left execution
  • pre-silicon execution
  • SoC integration
  • SoC delivery and bring-up
  • system-level direction
  • execution standards
  • debug strategies
  • SoC environments
  • technical leadership role
  • hands-on contribution
  • mentoring and coordination
  • supporting individual contributors
  • scaling DDR Shift Left capabilities
  • sustainable, high-impact function
  • complex technical concepts
  • written, verbal, or visual means
  • documentation, presentations, trainings, and technical discussions
  • collaborate thoughtfully with engineers
  • experience levels
  • mentoring and knowledge sharing
  • inclusive, supportive team environment
  • SoC and IP blocks
  • SoC as a complete system
  • hardware (silicon), firmware, BIOS, and software
  • optimizing performance and power
  • IP and domain architects
  • complex technical issues and risks
  • architectural approaches
  • product requirements
  • Platform & System Architecture discussions and documentation
  • primary technical steward
  • architecture analysis and technical solutions
  • feature updates and change requests
  • Design teams
  • area and floorplan considerations
  • verification test plan reviews
  • timing targets
  • emulation plans
  • pre-silicon issue resolution
  • performance and power verification signoffs
  • post-silicon teams
  • debug and resolution of product performance, power, and functional issues
  • Systems and SoC architecture
  • CPU or GPU, memory subsystems, fabrics, CPU/GPU coherency, multimedia, I/O subsystems, clocks, resets, virtualization, or security
  • analyzing CPU-, GPU-, or system-level micro-architectural features
  • performance characteristics across workloads
  • power management microarchitecture
  • low-power design
  • power optimization
  • power impact at the architecture, logic design, and circuit levels
  • Clear, effective communication and collaboration skills
  • work across disciplines and experience levels
  • architects and engineering partners
  • teams and geographies
  • inclusive and respectful working style
  • computer engineering, Electrical Engineering, or equivalent practical experience