In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
You will be part of a silicon design team developing cutting-edge ASICs used to accelerate machine learning computation in data centers. You will help us push the boundaries of silicon interface technology. Your contributions will help shape future generations of data center ML accelerators.
As part of the TPU interface design team, you will play a pivotal role in pushing the boundaries of technology to improve the performance and power of our TPUs. You will drive the selection, integration, and execution of mixed signal IPs. In this highly cross-functional role, you will be tasked with specifying and meeting the technical requirements and coordinating all aspects of the IP integration across all phases of the silicon lifecycle.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Drive Mixed Signal IP selection and procurement.
- Own Mixed Signal IP planning and roadmap definition.
- Coordinate pre-silicon integration strategy of Mixed Signal IPs.
- Coordinate Mixed Signal IP implementation with cross-functional teams (e.g., Design, Verification, Physical Design, DFT, Post-Silicon).
- Assist in post silicon bring-up and validation of Mixed Signal IPs.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of silicon engineering experience.
- Experience designing or integrating analog PHY designs (e.g., PCIe, UCIe, or HBM PHYs).
- Experience with design integration flows and requirements.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of silicon engineering experience.
- Experience designing or integrating analog mixed signal designs (e.g., high speed IOs, sensors, PLLs, etc.).
- Experience writing design specifications.
- Experience coordinating designs through the entire silicon product lifecycle.
- Ability to coordinate execution across multiple cross-functional teams.