Mixed Signal / Pll Post - Silicon Validation Engineer

AMD AMD · Semiconductors · Folsom, CA · Engineering

AMD is seeking an experienced Mixed Signal/PLL Post-Silicon Validation Engineer to join their PLL design team. The role involves defining, specifying, and implementing advanced PLL IPs. Responsibilities include designing complex building blocks, running pre-tapeout verification, working with mask design and characterization groups, and leading/mentoring junior engineers. The position requires strong knowledge of mixed-signal circuit design, FinFET technology, PLLs, and standard design tools, with proficiency in scripting languages like Python and Perl being a plus.

What you'd actually do

  1. Design of complex building blocks of a PLL including architecture development and transistor level circuit design
  2. Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
  3. Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
  4. Lead/mentor junior engineers

Skills

Required

  • Mixed Signal Circuit Design
  • PLLs
  • FinFET technology
  • VCO
  • Adaptive Clocking charge-pump
  • dividers
  • state machines
  • LDO
  • feedback and compensation techniques
  • bandgap
  • TDC
  • interpolator circuits
  • high speed buffers
  • analog circuit design
  • Physical design
  • STA
  • methodology scripts (Tcl)
  • Cadence custom circuit design tools (ADE-L, ADE-XL)
  • Spectre
  • Hspice
  • AFS
  • DRC
  • LVS
  • Calibre
  • ICV

Nice to have

  • Perl
  • Python
  • MATLAB
  • System Verilog
  • Digital PLL techniques
  • TDC or DSP and control theory experience related to digital PLLs
  • Dual charge-pump PLL designs
  • Fractional-N PLLs
  • spread-spectrum PLLs
  • Monte-Carlo simulations
  • noise simulations
  • aging simulations
  • EM simulations
  • IR drop simulations
  • stability analysis
  • Helic/EMX
  • scripting languages
  • analytical/problem solving skills
  • attention to details

What the JD emphasized

  • Solid knowledge Mixed Signal Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, Adaptive Clocking charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.
  • Solid knowledge of industry standard tools and practices for analog circuit design
  • Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
  • Must be a self-starter, and able to independently drive tasks to completion