Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for defining the top-level SoC architecture and chiplet strategy for our next-generation Machine Learning (ML) accelerators. This role requires deep expertise in SoC design, chiplet integration, and ML-specific hardware.
Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority.
We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $256000 - $279000 (USD) + 20% bonus target
Learn more about benefits at Google.
Responsibilities
- Define and own the Chip/IP architectures for next-generation ML accelerators.
- Lead the architecture and design of the chip top-level, managing interfaces, clocking, power, and integration of all major IP blocks.
- Architect specific accelerator components and chiplets.
- Collaborate with micro-architecture and physical design teams to ensure a feasible and optimal design, making trade-offs in performance, power, and area (PPA).
- Work with systems and software teams to ensure the SoC architecture meets product requirements.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 10 years of experience in system on a chip (SoC) architecture or micro-architecture.
- Experience with hardware building blocks for machine learning (ML) accelerators (e.g., matrix multiply units, vector engines, or attention mechanisms).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with chiplet-based designs and high-speed die-to-die interconnects (e.g., UCIe, CXL).
- Knowledge of high-performance and low-power architectures for ML acceleration.
- Understanding of the full ASIC design flow (e.g., RTL, verification, synthesis, PD).