Package Design Rule Owner (dro)

Intel Intel · Semiconductors · Arizona, Phoenix, United States

Seeking an experienced Package Design Rule Owner (DRO) to define, validate, and deploy design rules for package substrate design, collaborating with product design, manufacturing, and assembly teams to ensure competitive product designs that meet cost and manufacturability requirements. The role involves working from early technology stages through product design tape out, driving a consistent Design Rule strategy and a forward-looking roadmap, and interacting with cross-disciplinary stakeholders, external suppliers, and customers.

What you'd actually do

  1. The Package Substrate Design Rule Owner (DRO) is responsible for definition, validation and deployment of design rules for package substrate design.
  2. The DRO collaborates with product design, substrate manufacturing and package assembly to identify and drive design rules that enable competitive product designs that meet cost and manufacturability requirements.
  3. A key part of this role is being involved from the earliest stages of technology and product concept through to product design tape out.
  4. The DRO works across product families to drive a consistent Design Rule strategy and a forward-looking, industry-leading Design Rule roadmap.
  5. This position involves working with cross-disciplinary and cross-organizational stakeholders and interfacing directly with product designers.
  6. Interaction with external suppliers and customers can also be expected in this role.

Skills

Required

  • Bachelor's degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Material Science, or a related STEM field.
  • 6+ years of experience with a Bachelor's degree, 4+ years with a Master's degree, or 2+ years with a PhD.
  • 2+ years in semiconductor fabrication processes and packaging technologies.
  • 2+ years of experience in package substrate physical design, or thermo-mechanical and electrical performance, or substrate manufacturing and assembly process or a combination of these areas.

Nice to have

  • Active US Government TS/SCI Security Clearance with Polygraph.
  • Expertise in advanced packaging architectures such as EMIB and Foveros.
  • 5+ years of strong analytical and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions.
  • Ability to work independently and at various levels of abstraction
  • 5+ years of strong organization, time management, and communication skills and self-motivated individual.
  • Good understanding of IC Packaging
  • Strong Communication skills and the ability to work with others

What the JD emphasized

  • US Citizenship is required.
  • Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.