Packaging Design Engineer at AMD

What you'd actually do

A packaging design engineer who has experiences on substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design.

Come up with performance metrics for organic package technologies in order to design high speed chips and systems

Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging.

Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size

Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.

Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage.

Skills

Required

substrate layout design
ballmap assignment
high speed interface design
advanced PKG (2.5D/3D PKG) design
low-cost PKG solution design
Cadence package design tool

Nice to have

FPGA IP understanding
electrical requirements translation
cost-effective and manufacturable solutions
performance metrics definition
routing and placement studies
script development
DFx requirement understanding
organic/PCB technologies understanding
high power, Gbs IO products experience
SKILL knowledge
2D/3D package design and modeling tools (Ansys, AutoCAD)
DoE, DFM/DFR knowledge
SerDes design knowledge
package/PCB layout constraints knowledge

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. **Together, we advance your career. **

THE ROLE:

The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.

THE PERSON:

This is a high visibility position working on custom ASIC packages that include FPGA IP. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.

KEY RESPONSIBILITIES:

A packaging design engineer who has experiences on substrate layout design, ballmap assignment in terms of PCB design requirement, high speed interface (PAM-4 112Gbps/high speed DDR) design practices, advanced PKG (2.5D/3D PKG) design knowledge, low-cost PKG solution design including FCCSP, InFO, and thin-core design.
Come up with performance metrics for organic package technologies in order to design high speed chips and systems
Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging.
Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.
Support substrate layout review and work with layout designer to achieve electrical performance and DFx requirement during the design stage and final design review stage.

PREFERRED EXPERIENCE:

Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines
Package/PCB layout experience. Experience in high power, Gbs IO products is a plus.
Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.
Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.
Knowledge on DoE, DFM/DFR is a plus.
Good knowledge of SerDes design and package/PCB layout constraints

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-SH1

#LI-HYBRID

_Benefits offered are described: _AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

_ _

This posting is for an existing vacancy.