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**Packaging Design Engineer **
**THE ROLE: **
The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.
THE PERSON:
This is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements, implement Package/Module physical design, layout, optimization/iterations, verification, design rule checks for manufacturability and signoff. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.
KEY RESPONSIBILITIES:
Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off
Work on DoE, keeping upto date DFM/DFR for the product designs
Package/PCB layout and proficient use of Cadence (Advanced Package Designer APD/SIP, PCB Editor) or Mentor Xpedition design tools
Building on design rules used in previous generations of high power, Gbps IO products.
Use scripting languages (PERL, Python, TCL, Shell etc), efficient tools in Unix/Windows environment to develop automation methodology
Use analytical and simulation tools to document package/module design
requirements (technology, stackup etc) in the project conception stages
and negotiate design rules with package technologists and vendors
Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging.
Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.
PREFERRED EXPERIENCE:
- Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines
- 4+ yrs of working experience of 2D/3D package electrical modeling tools, such as Cadence, Ansys, AutoCAD is a plus
- Good knowledge of SerDes design and package/PCB layout constraints
- Conduct package design reviews, working knowledge of Valor/Calibre
- Mentor junior package designers in the group
ACADEMIC CREDENTIALS:
- Bachelor’s or Master's degree in Engineering
**LOCATION: **Hyderabad, TN, India
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_Benefits offered are described: _AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.