Packaging Engineer

AMD AMD · Semiconductors · Hsinchu, Taiwan · Engineering

This role is for a Packaging Engineer at AMD, focusing on bringing up and sustaining various package types for AMD products, including those for AI and data centers. The responsibilities include manufacturing readiness, yield, quality, cost improvements, process standardization, and supplier management. While the company works on AI products, this specific role is in hardware packaging engineering, not directly building AI models or systems.

What you'd actually do

  1. Responsible for InFO, WFB/CoWoS-L, CoWoS, WLFO, FCBGA, LGA and Chiplet package Manufacturing readiness for New Product bring up at manufacturing site.
  2. Responsible for packaging yield, quality, cost and operation productivity improvements and sustaining activities.
  3. Drive assembly process baseline standardization and continuous improvement.
  4. Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack.
  5. Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products

Skills

Required

  • InFO, EFB/CoWoS-L,CoWoS-S, WLFO, FCBGA, LGA and chiplet package functions
  • packaging yield, quality, cost and operation productivity improvements
  • assembly process baseline standardization
  • packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack
  • process, equipment & material capability
  • NPI and Ramp Up readiness
  • performance of assembly manufacturing site/supplier
  • strategic supplier management
  • change management
  • DOE and JMP
  • MS degree in Mechanical or Material or Chemical Engineering
  • Fluent in both spoken and written English

Nice to have

  • program management experience
  • team player
  • cross functional project management skill
  • strong interpersonal skills
  • good communication & presentation skills
  • Lead and manage team experience
  • Strategic supplier management experience
  • Creative, highly motivated self-driven individual team player
  • demonstrated ability to independently complete complex engineering tasks on/ahead of time
  • Lead & Drive for solutions
  • aptitude to thrive in a fast-paced multi-tasking environment
  • Preparing reports /Presentation
  • ability to communicate Root cause and Resolution effectively
  • Creative, self-driven, highly motivated individual
  • demonstrated ability to independently manage complex engineering tasks
  • Strong interpersonal communication, analytical, project management, task & time management
  • excellent communication skills
  • managing horizontally across multiple internal functional organization
  • semiconductor engineering environment
  • NPI to HVM experience

What the JD emphasized

  • min 8 years’ experience in InFO or 2.5D/3D Bump/TSV/Packaging, Flip Chip BGA/LGA or WLFO process engineering with min total 7 years assembly work experience