Packaging Engineer (based in Kaohsiung)

AMD AMD · Semiconductors · Hsinchu, Taiwan · Engineering

This role is for a Packaging Engineer at AMD, focusing on manufacturing readiness, yield, quality, and cost improvements for various advanced package types including InFO, CoWoS, FCBGA, LGA, and chiplets. The candidate will work closely with cross-functional teams and suppliers to drive process standardization, new product bring-up, and sustaining activities in a manufacturing environment. Experience in semiconductor packaging processes and project management is required.

What you'd actually do

  1. Responsible for InFO, WFB/CoWoS-L, CoWoS, WLFO, FCBGA, LGA and Chiplet package Manufacturing readiness for New Product bring up at manufacturing site.
  2. Responsible for packaging yield, quality, cost and operation productivity improvements and sustaining activities.
  3. Drive assembly process baseline standardization and continuous improvement.
  4. Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, Functional Test and Mark/Pack.
  5. Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products

Skills

Required

  • InFO, EFB/CoWoS-L,CoWoS-S, WLFO, FCBGA, LGA and chiplet package functions
  • Program management experience
  • Cross functional project management skill
  • Interpersonal skills
  • Communication & presentation skills
  • English (written and spoken)
  • Manufacturing readiness for New Product bring up
  • Packaging yield, quality, cost and operation productivity improvements
  • Assembly process baseline standardization
  • Continuous improvement
  • Packaging interaction activities
  • Process, equipment & material capability enhancement
  • NPI and Ramp Up readiness
  • Supplier management
  • Change management
  • DOE and JMP
  • MS degree in Mechanical or Material or Chemical Engineering
  • Semiconductor engineering environment
  • NPI to HVM experience

Nice to have

  • Lead and manage team experience
  • Strategic supplier management experience
  • Creative, highly motivated self-driven individual team player
  • Ability to independently complete complex engineering tasks on/ahead of time
  • Lead & Drive for solutions
  • Aptitude to thrive in a fast-paced multi-tasking environment
  • Preparing reports /Presentation
  • Ability to communicate Root cause and Resolution effectively
  • Strong interpersonal communication
  • Analytical
  • Task & time management
  • Managing horizontally across multiple internal functional organization

What the JD emphasized

  • min 8 years’ experience in InFO or 2.5D/3D Bump/TSV/Packaging, Flip Chip BGA/LGA or WLFO process engineering with min total 7 years assembly work experience
  • Possess InFO, Chiplet packaging, 2.5D/3D TSV/Packaging, Flip Chip BGA/LGA process knowledge and Chip-Packaging Interaction knowledge