Pcie / Cxl and Hsio Validation Engineer

AMD AMD · Semiconductors · Austin, TX · Engineering

This role is for a Principal Validation Engineer focused on PCIe, CXL, and HSIO interfaces for AMD's datacenter CPU post-silicon validation. Responsibilities include developing and executing test plans, creating test content, developing validation infrastructure, debugging issues, and collaborating with cross-functional teams. The role requires experience with high-speed IO interfaces, silicon bring-up, and programming/scripting languages.

What you'd actually do

  1. Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IO
  2. Develop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testing
  3. Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
  4. Test interactions between various SoC features using validation infrastructure
  5. Debug and drive root-cause analysis for SoC related issues

Skills

Required

  • PCIe Gen5/6+
  • CXL
  • UCIe
  • inter-die interfaces
  • multi-socket server interface
  • SoC validation
  • system-level validation
  • debug skills at SoC and system level
  • programming/scripting language (C/C++, Python, Perl, ...)
  • Server OSes (Linux, Windows)
  • common lab equipment (protocol/logic analyzers, oscilloscopes)
  • board/platform-level debug
  • system architecture
  • technical debug
  • validation strategy
  • analytical/problem-solving skills
  • attention to details

Nice to have

  • Understanding of modern x86 microprocessor architecture
  • Server platform architecture
  • Test plan and workload development experience
  • Participated in silicon bring up and debug
  • support to internal engineering teams
  • Able to execute and drive success of programs with multiple projects on the go
  • Forward thinker that drives improvement to development process, code architecture and fosters a spirit of innovation and continuous improvement
  • Strong verbal and written English communication skills

What the JD emphasized

  • Proven hands on experience in soc design or validation of high speed IO interfaces
  • Has experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both.
  • Must be a self-starting team player with excellent communication skills who can work with minimal guidance
  • Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
  • Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization
  • Extensive knowledge of system architecture, technical debug, and validation strategy