Pdk Lvs Development Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Develop and maintain Process Design Kits (PDKs) for semiconductor manufacturing, focusing on physical verification runsets (DRC/LVS/PERC) using EDA tools like Calibre/ICV/Pegasus. This role involves scripting, collaboration with technology and EDA partners, and ensuring the quality and operability of PDK collaterals for Intel's product design teams.

What you'd actually do

  1. Develop PDK physical verification runset (DRC/LVS/PERC) in Calibre/ICV/Pegasus.
  2. Ensuring seamless operability of LVS-Parasitic Extraction flow.
  3. Collaborate with technology specification owners, validation teams, process development teams, and EDA vendors to ensure high-quality solutions.
  4. Drive the adoption of industry-standard methods and facilitate ease of use for internal and external design communities.
  5. Develop and implement QA and regression solutions to qualify the PDK collaterals.

Skills

Required

  • Bachelor's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field, with 6+ years of experience; or Master's degree with 4+ years of experience; or PhD with 2+ years of experience.
  • Expertise in DRC and LVS, in one of the following EDA verification tool: ICV-PXL, Calibre-SVRF, or Pegasus runset development.
  • Expertise in PERC verification development.
  • Expertise in scripting languages such as Perl, Python, or TCL.
  • Experience with EDA tools, such as Virtuoso, Custom Compiler.

Nice to have

  • 3+ years of experience developing PDKs for advanced process technologies.
  • Familiarity with IC physical design, layout, and verification flows.
  • Knowledge of IC manufacturing process flows and DA/CAD/CAE environments.
  • Strong problem-solving skills and the ability to drive improvements across tools and methodologies.

What the JD emphasized

  • Expertise in DRC and LVS, in one of the following EDA verification tool: ICV-PXL, Calibre-SVRF, or Pegasus runset development.
  • Expertise in PERC verification development.