Phy Technology Enablement Engineer

Intel Intel · Semiconductors · Haifa, Israel

This role focuses on enabling next-generation high-speed I/O technologies by leading PHY and SerDes IP validation and integration for future platforms. Responsibilities include pre-silicon validation of PHY IPs for standards like PCIe Gen7 and Ethernet 1.6T, evaluating internal and third-party IPs, defining IP requirements, developing integration guidelines, and debugging test chips. Requires a Bachelor's degree in Electrical Engineering with 3+ years of experience in electrical validation and debugging, and a solid understanding of SerDes architectures.

What you'd actually do

  1. Lead pre‑silicon validation of high‑speed I/O PHY IPs for next‑generation standards (PCIe Gen7, Ethernet 1.6T, DDR6)
  2. Evaluate internal and third‑party PHY IPs against product, system, and roadmap requirements
  3. Define IP requirements, drive vendor engagement, and influence IP selection decisions
  4. Develop and review PHY integration and architectural guidelines
  5. Lead debug and validation of high‑speed I/O test chips, resolving complex signal integrity and implementation issues

Skills

Required

  • Bachelor's degree in Electrical Engineering
  • 3+ years of relevant experience
  • pre-silicon validation
  • post-silicon electrical validation
  • debugging
  • SerDes architectures
  • high-speed I/O design principles
  • troubleshoot complex hardware issues
  • communication skills
  • collaboration skills

Nice to have

  • Experience with IEEE, PCIe SIG, or LPDDR standards activities
  • Familiarity with emerging interconnect standards (CXL, UALink, PCIe Gen7)
  • Background in post-FEC analysis
  • advanced signal integrity