Physical Design Engineer

NVIDIA NVIDIA · Semiconductors · Shanghai, China +1

Physical Design Engineer role at NVIDIA, contributing to GPU and Mobile chip designs using advanced process technology and EDA tools. Responsibilities include floorplanning, power/clock distribution, timing optimization, place & route, timing closure, SI analysis, and physical verification. Requires 2+ years of experience with EDA tools like Synopsys and Cadence, and expertise in clock/power distribution, P&R, timing closure, RC extraction, and verification on advanced nodes.

What you'd actually do

  1. A role in physical design for NVIDIA GPU and Mobile chips.
  2. Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification.
  3. Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

Skills

Required

  • BS in Engineering or Science or equivalent experience
  • Power user of EDA tools from Synopsys (ICC2/FC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus)
  • Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes
  • 2+ years of experience in above areas

Nice to have

  • MS in Engineering or Science
  • Knowledge in FinFET technology, circuit design, and package design
  • Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre)
  • Proficiency in Perl, Python, TCL and Makefile scripts

What the JD emphasized

  • Power user of EDA tools from Synopsys (ICC2/FC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus)
  • Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes
  • 2+ years of experience in above areas