Physical Design Engineer

AMD AMD · Semiconductors · VANCOUVER, BC · Engineering

This role is for a Physical Design Engineer at AMD, focusing on improving Performance, Power, and Area (PPA) for next-generation graphics processor IP. The engineer will collaborate with RTL, Physical Design, Methodology, and CAD teams to translate architectures into silicon, influencing design decisions from concept to tape-out. Responsibilities include driving PPA improvements, optimizing memory placement and synthesis recipes, resolving bottlenecks, exploring area/power savings, optimizing tools/flows, and delivering best-known recipes. Preferred experience includes ASIC Physical Design, RTL analysis, timing analysis, library understanding, experience with low-voltage design and STA correlation, and experience with taping out advanced SOC nodes. The role also involves mentorship.

What you'd actually do

  1. Lead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams.
  2. Study block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.
  3. Work with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.
  4. Collaborate with RTL designers to explore additional opportunities for area and power savings.
  5. Partner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA.

Skills

Required

  • Verilog
  • Timing Analysis
  • library understanding
  • design margining methodology
  • low voltage design
  • silicon – STA correlation
  • Synopsys
  • Cadence
  • Mentor Graphics
  • communication skills
  • time management skills
  • presentation skills
  • analytical skills
  • problem solving skills
  • attention to detail skills
  • self-starter
  • independent task completion
  • mentorship
  • team player
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • RTL analysis skills

What the JD emphasized

  • next-generation graphics processor IP
  • PPA outcomes
  • concept to tape-out
  • modern processor architectures
  • complex design challenges
  • driving results
  • technical excellence
  • ASIC Physical Design from RTL to GDSII
  • taping out 3nm, 5nm, 7nm and/or 16nm SOC