Physical Design Engineer, Annapurna Labs

Amazon Amazon · Big Tech · Cupertino, CA · Applied Science

The role focuses on the physical design and optimization of hardware, specifically custom SoCs (System on Chip) that are central to AWS Machine Learning servers, including AWS Inferentia and Trainium Systems. The engineer will be involved in the entire physical design flow from synthesis to sign-off, developing methodologies, and evaluating third-party IP. While the hardware supports AI/ML workloads, the core craft of the role is in ASIC physical design engineering, not in building or researching AI models themselves.

What you'd actually do

  1. Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
  2. Drive IO/Core block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
  3. Develop physical design methodologies
  4. Evaluate 3rd party IP and provide recommendations

Skills

Required

  • Bachelor's degree in Electrical Engineering or a related field
  • Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
  • Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing

Nice to have

  • Master's degree in Electrical or Communications Engineering or a related field
  • Experience with formal verification techniques including abstraction and end-to-end checking
  • Experience with ARM and various DSP ISAs
  • Experience with current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards
  • Experience with industry standard tools and scripting languages (Python or Perl) for automation