Physical Design Engineer

Intel Intel · Semiconductors · Penang, Malaysia

Physical Design Engineer responsible for the implementation of custom IP and SoC designs from RTL to GDS, covering synthesis, place and route, timing analysis, and verification for Intel's advanced process nodes.

What you'd actually do

  1. Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
  5. Optimizes design to improve product level parameters such as power, frequency, and area.

Skills

Required

  • 1 years of relevant experience in silicon design/Physical design and/or TFM development
  • Scripting skills using a programming language such as Perl, TCL, or Python
  • Use of industry standard placement and routing CAD tools

Nice to have

  • Floor planning and power grid setup
  • Clock methodologies
  • IR droop and SI mitigation strategies
  • power and timing signoff conditions
  • layout and reliability verification
  • VLSI circuits
  • design techniques
  • sub-micron CMOS technologies
  • Logic synthesis
  • automated place and route tools
  • Logic equivalent verification debugging
  • Logic design fundamentals