Physical Design Engineer, Floorplan, Google Cloud

Google Google · Big Tech · Bengaluru, Karnataka, India

This role is for a Physical Design Engineer focused on developing custom silicon solutions (ASICs) for accelerating machine learning computation in data centers. The engineer will be responsible for physical design partitions, driving timing and power closure, and contributing to design methodology. While the silicon accelerates ML, the role itself is in hardware design and engineering, not direct AI/ML model development or deployment.

What you'd actually do

  1. Take ownership of one or more physical design partitions or top level.
  2. Drive to the closure of timing and power consumption of the design.
  3. Contribute to design methodology, libraries, and code review.
  4. Define the physical design related rule sets for the functional design engineers.

Skills

Required

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience
  • 4 years of experience with physical design
  • Experience in block-level synthesis, floor-planning, place-and-route, clock tree synthesis (CTS), timing closure, and power analysis
  • Experience with System on a Chip (SoC) cycles

Nice to have

  • Master’s degree in Electrical Engineering
  • Experience in coding with System Verilog and scripting with TCL
  • Experience with layout verification and design rules
  • Experience in VLSI design in SoC
  • Experience in using physical design tools like Place and Route tools (P&R), Static Timing Analysis (STA) tools, and physical verification tools

What the JD emphasized

  • 4 years of experience with physical design
  • Experience in block-level synthesis, floor-planning, place-and-route, clock tree synthesis (CTS), timing closure, and power analysis
  • Experience in using physical design tools like Place and Route tools (P&R), Static Timing Analysis (STA) tools, and physical verification tools