Physical Design Engineer for Core Ip

Intel Intel · Semiconductors · Oregon, Hillsboro, United States

Physical Design Engineer for Core IP at Intel, responsible for the implementation of custom CPU designs from RTL to GDS, including synthesis, place and route, timing analysis, and verification. The role involves optimizing CPU designs for power, frequency, and area, and working with EDA vendors to enhance tool capabilities.

What you'd actually do

  1. Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  5. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU.

Skills

Required

  • Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 2 + years of relevant work experience
  • 2+ years' experience in Synthesis of a digital logic block or partition
  • 2+ years of experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
  • 2+ years of experience in PV convergence (including static timing and power analysis)
  • 2+ years of experience in Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks
  • Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)

Nice to have

  • Strong knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution
  • Strong knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques
  • Strong knowledge of RTL to GDS methodologies and formal equivalence
  • Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)
  • Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores.
  • Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.