Physical Design Engineer- Foundry Services

Intel Intel · Semiconductors · Arizona, Phoenix, United States

Physical Design Engineer for Intel Foundry Services, focusing on Si Interposer and Bridge designs. Responsibilities include full physical design flow (floor planning, place and route, verification, analysis), optimization for performance/power/area, and methodology development. Requires a Bachelor's or Master's degree in Electrical Engineering or related field with significant experience in EDA tools and physical design aspects.

What you'd actually do

  1. Perform physical design implementation of Si Interposer designs, progressing from Floor planning on to create a database ready for manufacturing.
  2. Conduct all aspects of the physical design flow, including place and route, floor planning, Routing and Physical design verification.
  3. Execute Signal Integrity analysis, power analysis, and reliability analysis to ensure design integrity.
  4. Perform verification and signoff, including formal equivalence verification, reliability verification, layout verification, electrical rule checking, and structural design checking.
  5. Analyze results of verification efforts, recommending and implementing fixes for violations.

Skills

Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience, or Master's degree with 3+ years of experience
  • Experience in EDA tools for custom physical design and Auto-place-n-route, including virtuoso, Innovus or ICC/ICC2/fusion, icvalidator or calibre, UPF, RTL, SPICE, OASIS, and ODB++
  • Experience with physical Design including at least 2 of the following: floor planning, route optimization/shielding and Signal Integrity analysis, power delivery design/analysis for multi-power domains and reliability verification.
  • Full chip physical design completion and verification for tapein/tapeout

Nice to have

  • Experience optimizing designs for signal integrity and power integrity
  • Experience in chip-level design and tape-in assembly for advanced technology nodes.

What the JD emphasized

  • US Citizenship
  • Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph