Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Amazon Amazon · Big Tech · Cupertino, CA · Software Development

This role is for a Physical Design Engineer focused on Static Timing Analysis for hardware used in AWS data centers, including machine learning inference products like AWS Inferentia. The engineer will develop and maintain analysis flows, write and validate timing constraints, debug timing issues, and automate reporting. While the hardware supports AI products, the role itself is focused on the physical design and timing analysis of the hardware, not the AI/ML models themselves.

What you'd actually do

  1. Develop & maintain flows for block and full-chip level static timing analysis
  2. Write, debug & validate timing constraints for blocks and full-chip.
  3. Run Static Timing Analysis and give frequent feedback to team members and leads.
  4. Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).
  5. Develop scripts to automate running timing analysis and generate reports.

Skills

Required

  • Experience scripting or coding
  • BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS
  • Expertise in timing analysis fundamentals
  • 1+ years doing Static Timing Analysis
  • 1+ years with timing constraint development
  • Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others)
  • Understanding of ASIC Physical Design from RTL-to-GDSII
  • Understanding of other sign-off activities (ir/em, physical verification, DFT)
  • 1+ years of scripting experience with Tcl, Perl or Python

Nice to have

  • Experience in mentoring, leading and coaching
  • Expertise developing flows using STA tools (examples: PrimeTime, Tempus or others)
  • Expertise in ECO flows (examples: PT-DMSA, Tempus-ECO, Tweaker or others)
  • Experience in advanced nodes - 16nm or below
  • Expertise in parasitic extraction tools (examples: STAR-RC, Quantus or others)
  • Expertise on circuit level analysis using tools like SPICE / SPECTRE
  • Experience with timing of IO interfaces like DDR, HBM, PCIe, Die-to-Die etc.