Physical Design Power Optimization Engineer

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel +1

NVIDIA is seeking a Physical Design Power Optimization Engineer to join their Networking Silicon Power engineering team. The role involves optimizing power for high-speed communication devices and chips, covering aspects from RTL to GDS, including synthesis, power distribution, place and route, timing closure, and power/noise fixes. Responsibilities also include power estimation and modeling.

What you'd actually do

  1. Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
  2. Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
  3. Power estimation and power modeling.

Skills

Required

  • B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering
  • 2+ years of experience in physical design and/or BE power optimization aspects
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)

Nice to have

  • Knowledge in physical design flows and methodologies (PNR, STA, physical verification)
  • FE design experience