Physical Design Signoff Cad Engineer

NVIDIA NVIDIA · Semiconductors · Yokneam, Israel

NVIDIA is seeking a Physical Design Signoff CAD Engineer to join their Networking Silicon engineering team. The role involves developing physical design, STA, Logic eq, and Power Integrity flows and methodologies for networking chips and SOCs. Responsibilities include collaborating with block owners and STA engineers, developing flow and tool methodologies for timing analysis, power analysis, and back-end verification.

What you'd actually do

  1. You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
  2. Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
  3. Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
  4. Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.

Skills

Required

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience)
  • 2+ years of fulltime relevant experience
  • Physical Design
  • Backend CAD (Computer-Aided Design)
  • STA (Static Timing Analysis) and Timing closure methodologies
  • Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation)
  • Self-motivation
  • attention to detail
  • good written, verbal, and presentation skills
  • Strong sense of ownership
  • self-learning skills
  • ability to work both independently and collaboratively

Nice to have

  • Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality)
  • Knowledge in Tcl/Perl/Python

What the JD emphasized

  • critical to success in this role