Post Silicon Validation Manager

AMD AMD · Semiconductors · Bangalore, India · Engineering

This role is for a Post Silicon Validation Manager at AMD, responsible for planning and executing post-silicon validation for various IPs. The role involves leading a team, defining roadmaps, process improvements, and ensuring timely delivery of test cases and reports. It requires strong technical depth in post-silicon validation and experience with high-speed I/Os, power management, and measurement techniques. While the company mentions AI and its future, this specific role focuses on hardware validation, not AI model development or deployment.

What you'd actually do

  1. Take responsibility for the Post silicon validation scope and plan for IPs like HSIO, Memory, RAS, Cores, LSIO, Power Management, Multimedia etc.
  2. Ensure robust planning at the pre-silicon stage, working with DV or Emulation teams and support the Leads and engineers in framing the relevant test cases
  3. Support the team with the right infrastructure at the right time
  4. Define the scaling of the teams for Capability and Capacity in line with the BU’s growth
  5. Bigger picture planning for roadmaps and process improvements

Skills

Required

  • Post silicon validation scope and plan
  • Pre-silicon planning and test case framing
  • Team scaling and capacity planning
  • Roadmap and process improvement planning
  • Leadership and team culture development
  • Technical decision making in post silicon validation
  • Handling high performing technical teams
  • Post silicon validation of x86 IPs (Cores, Memory, RAS, HSIO)
  • Risk assessment and mitigation planning
  • Cross-functional stakeholder management (Enablement Manager, Leads, Program Managers, Product Managers, BIOS/FW Managers)
  • Experience with High Speed I/Os (PCIe Gen4+, DDR4/DDR5, LPDDR4/LPDDR5, USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces, Ethernet)
  • Power Management, Power Delivery, and Power Measurements
  • High speed and board measurement techniques
  • Use of high-end equipment (Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers)
  • Error-free and timely delivery of test cases and reports
  • Collaboration with Pre-silicon, DV, and other stakeholders
  • Defining and refining test plans
  • Debug & Triage of functional issues
  • Driving issue closure meetings and tracking schedules/metrics
  • Documentation and collateral delivery

Nice to have

  • Experience with scripting using TCL, Python
  • Experience working with cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW

What the JD emphasized

  • over 15 years of experience
  • handling high performing, dynamic and a strong technical team
  • post silicon validation of x86 IPs like Cores, Memory, RAS, HSIO
  • handling the growth charter for growing teams
  • calling out risks while anticipating issues and coming up with appropriate mitigation plans
  • working with the Enablement Manager and Leads, Program Managers, Product Managers, BIOS/FW Managers and other cross functional stakeholders
  • cross-functional teams like DV/Silicon Designers/Pre-silicon/Platform/BIOS/FW/ SW
  • High Speed I/Os like PCIe (preferably Gen4 and above), Memory (DDR4/DDR5.LPDDR4/LPDDR5), USB4.0/3.2/3.1, USB PD, USB Type C, Display interfaces and Ethernet and high-speed interconnects
  • Power Management, Power Delivery, and Power Measurements
  • high speed and board measurement techniques in using high end equipment like Oscilloscopes, Logic Analyzers, Debugger tools, Raspberry PI, Network analyzers, etc.
  • scripting using TCL, Python
  • error free and timely delivery of test cases and test reports, meeting or beating the program commitment
  • Synergize with the Pre-silicon and DV teams and other stakeholders for proper interception of milestones and risk callouts.
  • Actively participate in discussions with cross-functional teams in defining and refining test plans and guiding the team for the right path.
  • Be on top of all issues pertinent to Debug & Triage of any functional issues specific across the entire validation cycle
  • Drive meetings for issue closures and actively track schedules and milestone quality metrics
  • Ensure the Best in class Documentation and collateral delivery from the team.
  • Engage with the QA Validation and CAE teams for seamless handing over of test plans or reports, as relevant.