Power Architecture Engineer

NVIDIA NVIDIA · Semiconductors · Bangalore, India

NVIDIA is seeking a Power Architecture Engineer to work on end-to-end power aspects of their products, including ASIC power analysis, architecture, low power design, power-aware verification, and power correlation. The role involves architecting, developing, and verifying power estimation models and tools, designing system-level power features, and validating power features on silicon to improve performance per watt. Experience with VLSI circuits, digital design, low power techniques, and power estimation tools is required.

What you'd actually do

  1. Be part of NVIDIA Power Architecture Group that owns end-to-end power aspects such as - ASIC power analysis, power architecture, low power design, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's family of products.
  2. Contributing to power analysis by helping to architect, develop, verify & correlate power estimation models/tools for NVIDIA's products
  3. Be part of the team that architects & designs system-level power features for optimizing the dynamic and leakage power dissipation for different usecases.
  4. Work on power verification which includes structural, functional & power aware verification of power features of NVIDIA products by coming up with test plans, write testcases, build test bench components like Monitors, assertions and coverage points & own verification convergence across RTL, Gates and Silicon.
  5. Validate the effectiveness of the power features on silicon, conduct studies and contribute to the Performance/Watt improvement ideas.

Skills

Required

  • Power analysis
  • Power architecture
  • Low power design
  • Power-aware verification
  • UPF methodologies
  • Power correlation
  • Transistor-level leakage/dynamic characteristics of VLSI circuits
  • Digital design
  • Verilog
  • Low power design techniques (multi-VT, Clock gating, Power gating, Voltage Islands, DVFS)
  • Power estimation techniques, flows and algorithms
  • Power intent formats (UPF/CPF)
  • Static Power check tools (VCLP/CLP)
  • Dynamic Power verification tools (VCS-NLP)

Nice to have

  • Python programming
  • Object-oriented programming
  • Power analysis tools (PTPX, EPS)
  • Lab setups for power measurements (scope/DAQ)
  • Board level power issue analysis

What the JD emphasized

  • 1+ years of experience related to Power such as Power analysis, Power Design, Power Aware Verification, UPF methodologies and Power Correlation
  • Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits
  • Familiarity with low power design techniques such as multi-VT, Clock gating, Power gating, Voltage Islands and Dynamic Voltage-Frequency Scaling (DVFS)
  • Knowledge of power intent formats - UPF/CPF or similar
  • Experience in Static Power check tools like VCLP/CLP or similar & Dynamic Power verification tools like VCS-NLP or equivalent