Power Management & Memory Ip Design Verification Engineer, AI Hardware

Tesla Tesla · Auto · Palo Alto, CA · Tesla AI

Tesla's AI Hardware team is seeking a SOC Verification Engineer to verify power management subsystems and high-speed memory interfaces for AI inference chips used in FSD and Optimus. The role involves developing verification plans, test suites, and UVM-based environments using SystemVerilog/UVM, with a focus on ensuring functional correctness and protocol compliance for custom silicon.

What you'd actually do

  1. Develop and maintain verification plans for power management blocks and memory subsystems
  2. Verify power management digital logic
  3. Define and execute functional, corner case, and regression test suites
  4. Verify memory protocol compliance (timing, initialization, command/data integrity)
  5. Develop UVM-based environments for memory controller and PHY verification

Skills

Required

  • SystemVerilog/UVM
  • Power management concepts
  • Memory controller verification
  • Memory PHY verification
  • Protocol compliance
  • Verification planning
  • Test suite development

Nice to have

  • Mixed-signal verification using Verilog-AMS or Real Number Modeling
  • Power-aware simulation or emulation flows
  • JEDEC memory standards
  • Memory VIP

What the JD emphasized

  • Minimum 5+ years of relevant professional experience
  • Proficiency in SystemVerilog/UVM
  • Memory Interface/Controller Verification
  • Hands-on experience verifying high-speed memory controllers and/or PHY interfaces
  • Knowledge of JEDEC memory standards and protocol specifications