The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.
We are seeking a Senior Power Optimization Engineer to drive power reduction across the SoC. This role owns RTL-stage power analysis and optimization across our next-generation inferencing chip. You will use industry-leading EDA tools to find and implement power-saving opportunities including clock-gating refinement, operand isolation, datapath rebalancing, multi-bit flip-flop merging, and glitch reduction. You will help drive high-level architectural decisions based on their impact on power. You will work closely with architecture, physical design, design verification, and firmware teams to drive measurable per-block and system-level power reductions throughout the design cycle.
Responsibilities
- Drive RTL-stage power analysis and optimization using a combination of industry RTL power tools, internal metrics, and final PD power estimates, and turn findings into accepted RTL changes across the SoC
- Reduce switching activity and glitch power at RTL through clock-gating refinement, operand isolation, datapath rebalancing, and pipeline insertion
- Work closely with performance team to understand potential performance impact of proposed RTL changes and evaluate tradeoffs
- Work with subsystem owners to build representative activity vectors for AI inference workloads and use them to drive power analysis and signoff with PrimePower, PowerArtist, Joules, RedHawk-SC, or Voltus
- Collaborate with physical design on clock-tree power, multi-Vt mix, MBFF strategy, and EM and IR signoff feedback into RTL, and timing impact of proposed RTL power optimizations
- Partner with design verification on power-aware coverage and on representative workload stimulus for power closure
- Set and track per-block power budgets across the SoC and help determine useful metrics
- Influence next-generation chip planning through evaluation of new EDA capabilities and emerging RTL power optimization techniques
Requirements
- 5+ years ASIC/SoC RTL design experience on large multi‑billion‑gate SoCs with focus on power‑sensitive blocks and awareness of DFT impact on power
- Production experience with RTL power optimization using tools such as Synopsys PowerArtist, Cadence Joules, Synopsys PrimePower, or Siemens PowerPro
- Hands-on experience with switching-activity and glitch power analysis using SAIF or FSDB driven flows from RTL or post-synthesis simulation
- Strong knowledge of low‑power techniques including clock gating, multi‑Vdd, multi‑Vt, MBFF merging, operand isolation, UPF power‑intent flows and power-gating strategies
- Experience interfacing RTL design with synthesis, place and route, and signoff power flows including activity vector generation for representative workloads
- Familiarity with AI accelerator workloads including matmul and attention activity patterns, sparsity-aware power, DRAM and SRAM power dominance
- Experience driving RTL power reduction through multiple tape-out cycles with measured before-and-after power numbers
- Extensive RTL development using SystemVerilog/Verilog and scripting (Python/Tcl/Perl)
- Familiar with industry tools: PrimeTime, RedHawk‑SC or Voltus, and emulation‑driven activity capture
- Degree in Electrical Engineering, or equivalent experience
Compensation and Benefits
Benefits
Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:
- Medical plans > plan options with $0 payroll deduction
- Family-building, fertility, adoption and surrogacy benefits
- Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
- Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
- Healthcare and Dependent Care Flexible Spending Accounts (FSA)
- 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
- Company paid Basic Life, AD&D
- Short-term and long-term disability insurance (90 day waiting period)
- Employee Assistance Program
- Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
- Back-up childcare and parenting support resources
- Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
- Weight Loss and Tobacco Cessation Programs
- Tesla Babies program
- Commuter benefits
- Employee discounts and perks program