Pre-silicon Soc Modeling Engineer, Annapurna Labs Machine Learning Accelerators, Aws

Amazon Amazon · Big Tech · Cupertino, CA · Software Development

This role focuses on building and owning C++ models of custom System-on-Chips (SoCs) for AWS's machine learning accelerators (Trainium and Inferentia). The models are used by RTL designers, verification engineers, and software teams throughout the silicon development lifecycle, impacting chip design, verification, and production. The role involves translating architecture specs into C++ models, validating against RTL, developing test infrastructure, and contributing to performance modeling. While the chips are for ML accelerators, the core craft of this role is hardware modeling and verification, not direct AI/ML model development or research.

What you'd actually do

  1. Build and own models of SoC subsystems — translating architecture specs and RTL behavior into accurate, testable C++ models
  2. Work directly with RTL design and verification teams to validate model behavior against RTL, debug discrepancies, and support pre-silicon verification flows
  3. Develop model-based test infrastructure: regression suites, RTL correlation checks, and coverage-driven testing
  4. Contribute to performance modeling efforts — building cycle-approximate models that help architects evaluate design trade-offs before RTL exists
  5. Improve modeling methodology and infrastructure: how models are structured, integrated, tested, and released to DV and architecture teams

Skills

Required

  • Experience programming languages such as C/C++, Python, Java or Perl
  • 2+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
  • Familiarity with SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Nice to have

  • 2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
  • Experience working with DV teams or integrating models into verification flows
  • Experience with SystemC or TLM-based modeling
  • Experience correlating functional models against RTL simulation or emulation
  • Experience developing or calibrating performance models
  • Familiarity with Modern C++ (20 and beyond)
  • Experience with PyTest, GoogleTest, or similar test frameworks
  • Experience with multi-threaded simulation

What the JD emphasized

  • directly impact how our chips are designed, verified, and brought to production
  • bugs you catch save months of schedule and millions of dollars
  • own models that directly impact how our chips are designed, verified, and brought to production