Pre-silicon Validation Engineer

Intel Intel · Semiconductors · Bangalore, India

Intel is seeking a Pre-Silicon Validation Engineer with 7+ years of experience to join their Central Engineering Group in Bangalore, India. The role involves defining and executing verification plans, developing test benches, and debugging complex SoC designs using SystemVerilog and UVM. The engineer will collaborate with cross-functional teams to ensure high-quality SoC delivery and contribute to Intel's next-generation products.

What you'd actually do

  1. Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments to achieve required coverage levels and confirm adherence to microarchitecture specifications.
  2. Execute verification plans and system simulation models to analyze power, performance, and design functionality, uncovering and resolving bugs.
  3. Replicate, root cause, and debug issues in the presilicon environment, implementing corrective measures to address failing tests.
  4. Collaborate with SoC architects, microarchitects, RTL developers, postsilicon engineers, and physical design teams to enhance verification processes for complex architectural and microarchitectural features.
  5. Document test plans and lead technical reviews of plans and proofs with design and architecture teams.

Skills

Required

  • SystemVerilog
  • Universal Verification Methodology (UVM)
  • verification methodologies
  • directed and random test case development
  • debugging capabilities for SoC, fabric, memory subsystems, and protocols such as PCIe or Ethernet
  • microarchitecture concepts
  • advanced computer architecture
  • emulation and simulation tools for verification
  • power and performance analysis

Nice to have

  • SoC architectures
  • cache coherency protocols (e.g., CHI, IDI, UXI)
  • high-speed I/O subsystems
  • AMBA protocols
  • debugging tools
  • DSP algorithms
  • validation methods using MATLAB model
  • security validation flows
  • boot flows
  • fuse controllers
  • reset and clock validation
  • IP/Subsystem/SoC-level verification
  • coverage closure

What the JD emphasized

  • 10+ years of experience with a Bachelor's degree, 8+ years of experience with a Master's degree, or 7+ years of experience with a PhD.