Principal Asic Design Engineer - Pcie / High-speed I/o

AMD AMD · Semiconductors · Santa Clara, CA · Engineering

This role is for a Principal ASIC Design Engineer focused on high-performance network chips (AINIC and DPU) at AMD. The engineer will be involved in the front-end RTL design and integration of high-speed I/O subsystems, specifically PCIe. Responsibilities include collaboration with architecture, IP, and physical design teams, as well as post-silicon bring-up support. The role requires a Bachelor's or Master's degree in computer engineering or Electrical Engineering.

What you'd actually do

  1. PCIe architecture, design, and integration
  2. Front-end RTL design and integration of high-speed I/O subsystems
  3. Collaboration with architecture, IP, and physical design teams for first-pass silicon success
  4. Post-silicon bring-up support and yield learning

Skills

Required

  • Bachelors or Masters degree in computer engineering/Electrical Engineering
  • PCIe architecture, design, and integration
  • Front-end RTL design and integration of high-speed I/O subsystems
  • Collaboration with architecture, IP, and physical design teams
  • Post-silicon bring-up support and yield learning

Nice to have

  • Deep understanding of PCIe Transaction layer, Data Link layer, and Physical layer protocols and behaviors
  • Understanding of high-speed I/O (SerDes) architecture, design, and verification
  • Experience with VCS simulation tool, Perl/Python/Shell scripting, and SystemVerilog/Verilog RTL design