Principal Asic Engineer

Boeing Boeing · Aerospace · El Segundo, CA

Boeing is seeking a Principal ASIC Engineer to lead FPGA/ASIC designs for space, intelligence, and weapons systems. The role involves architectural definition, implementation, verification, and hardware integration of complex SoCs, collaborating with system engineers and managing design teams. Experience with SystemVerilog, UVM, and hardware emulation is preferred.

What you'd actually do

  1. Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones
  2. Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
  3. Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
  4. Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)
  5. Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed

Skills

Required

  • Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
  • 20 years of ASIC/FPGA design or verification experience
  • ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs
  • Professional experience with hardware-based integration and test of ASIC/FPGA designs
  • Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
  • Ability to obtain a US Security Clearance

Nice to have

  • Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
  • Experience with hardware emulators, especially Palladium
  • Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
  • Ability to executable test plans
  • Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
  • Ability to create self-checking and reusable testbenches from scratch
  • Experience developing Functional Coverage Models and Closing Code Coverage
  • Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
  • Proficient in scripting languages: Make, Perl, Python, etc.
  • Revision Control Systems: svn, cvs, git
  • Proficient in Linux Environments
  • Familiarity with space-based design techniques and radiation mitigation
  • Demonstrated history of 1st pass success with ASIC designs

What the JD emphasized

  • 20 years of ASIC/FPGA design or verification experience
  • ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs
  • Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders