Principal Cache Rtl Design - Cpu Team

AMD AMD · Semiconductors · Bangalore, India · Engineering

This Principal Cache RTL Design role at AMD focuses on the RTL design of high-performance x86-core ISA features, power management, cache, and coherency. It involves IP integration, sub-system level design, and optimization for power efficiency. The role requires extensive experience in digital IP/ASIC design, Verilog RTL development, and familiarity with the full IP design cycle, including verification, synthesis, and post-silicon validation. Leadership and mentoring of junior engineers are also key responsibilities.

What you'd actually do

  1. RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  2. Architect and design of power management features, cache, coherency.
  3. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  4. Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
  5. Lead design team from all aspects of the RTL deliverables.

Skills

Required

  • Verilog RTL development
  • Digital IP/ASIC design
  • RTL design verification
  • design quality checks
  • synthesis
  • timing closure
  • post silicon validation
  • front-end EDA tools sign-off and its flows
  • low power design and low power flow
  • scripting languages such as Python or Perl
  • prioritization and multi-tasking
  • digital design concepts

Nice to have

  • Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering
  • functional design verification or design

What the JD emphasized

  • 15+ years of experience in Digital IP/ASIC design and Verilog RTL development