Principal Electrical Engineer-fpga Verification

RTX RTX · Aerospace · tewksbury, MA +2 · Engineering

Principal Electrical Engineer focused on FPGA verification for radar applications, requiring expertise in SystemVerilog, UVM, and digital design verification methodologies. The role involves creating testbenches, tracking coverage, and documenting verification plans for control and signal processing radar systems.

What you'd actually do

  1. Own or contribute to the successful completion of FPGA-based designs, on time and on budget
  2. Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage using UVM
  3. Create complete documentation including verification plan and report
  4. Demonstrate self-motivation, with little supervision required
  5. Work cooperatively with systems, hardware, software engineers, and program management to ensure product success

Skills

Required

  • STEM degree
  • 8 years of prior relevant experience
  • Digital design verification
  • SystemVerilog
  • UVM-based testbenches
  • Constrained-random verification
  • Functional coverage methodology
  • AXI, PCIe, Ethernet, DDR protocols
  • Industry-standard simulators (Questa, VCS, Xcelium)
  • Regression management
  • Version control systems (Git, ClearCase, SVN)

Nice to have

  • Git (branching, pull requests)
  • UVMF
  • Vivado and Quartus simulation flows
  • Scripting languages (Python, Tcl, Perl)
  • VHDL
  • SLURM workload manager
  • Mentoring junior engineers
  • Existing DoD security clearance

What the JD emphasized

  • U.S. citizenship is required
  • Active and existing security clearance required after day 1
  • Digital design verification
  • Strong proficiency in SystemVerilog for both design and verification (interfaces, clocking blocks, assertions)
  • Hands-on experience building UVM-based testbenches from scratch, including env, agent, scoreboard, and coverage components
  • Solid understanding of constrained-random verification and functional coverage methodology