Principal Engineer, Design Verif Architecture

Intel Intel · Semiconductors · Penang, Malaysia

Principal Engineer in Design Verification Architecture at Intel, focusing on defining and architecting verification strategies and methodologies for silicon designs. Responsibilities include UVM testbench architecture, test strategy development, integration, and security validation. The role requires technical leadership and mentoring.

What you'd actually do

  1. Define and document verification strategies, methodologies, and solutions to achieve optimal silicon design implementation.
  2. Architect testbenches, applying UVM or formal-based verification approaches to ensure comprehensive design validation.
  3. Integrate block testbenches into chip-level UVM environments and verify seamless integration.
  4. Develop test strategies, architecture, and detailed test plans to validate design blocks against specifications.
  5. Collaborate with analog and digital teams to support post-silicon validation activities.

Skills

Required

  • System Verilog
  • UVM
  • validation protocols
  • validation strategies
  • IP/SoC integration
  • hardware simulation
  • debugging
  • validation environments
  • RTL design
  • microarchitecture fundamentals
  • test plans
  • test writing
  • validation tools

Nice to have

  • formal-based verification
  • security validation strategies
  • cross-functional initiatives
  • technical leadership
  • mentoring

What the JD emphasized

  • 12 or more years of experience in silicon design verification with a Bachelor's degree, or 8 or more years with a Master's degree, or 6 or more years with a PhD.
  • Proficiency in System Verilog and UVM-based methodologies for design verification.
  • Extensive knowledge of validation protocols, validation strategies, and IP/SoC integration.
  • Expertise in hardware simulation, debugging, and validation environments.
  • Strong understanding of RTL design and microarchitecture fundamentals.
  • Experience in developing test plans, test writing, and using validation tools and methodologies.
  • Demonstrated leadership in driving cross-functional initiatives and influencing technical direction within and beyond the organization.
  • Proven track record of mentoring technical leaders and cultivating a community of experts.
  • Experience in developing security validation strategies and enhancing security coverage in silicon designs.