Principal Engineer, Physical Design

Intel Intel · Semiconductors · Bangalore, India

Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

What you'd actually do

  1. Lead Structural Design / physical design Implementation of Custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
  2. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  3. Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  4. Analyzes results and makes recommendations to fix violations for current and future product architecture.
  5. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

Skills

Required

  • electrical / computer engineering, Computer Science, or in a STEM related field of study
  • leading small team of engineers
  • complex ASIC/SOC Implementation
  • system and processor architecture
  • designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller
  • System Verilog/SOC development environment
  • scripting languages (i.e. PERL, TCL, or Python)
  • Hardware validation techniques (i.e., formal Verification, Test and Function Verification)

Nice to have

  • Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
  • Industry standard protocols (i.e. PCIE, USB, DRR, etc)
  • interaction of computer hardware with software
  • Low power/UPF implementation/verification techniques
  • Timing Analysis / Physical Verification / Formal verification techniques

What the JD emphasized

  • 14+ years of experience with complex ASIC/SOC Implementation.