Principal Hardware Architect

Microsoft Microsoft · Big Tech · Hillsboro, OR +4 · Silicon Engineering

This role is for a Principal Hardware Architect responsible for designing and developing next-generation PCIe/CXL architecture for Microsoft Azure silicon platforms. The focus is on high-performance, scalable, and reliable I/O subsystems within the cloud infrastructure.

What you'd actually do

  1. Architecting and developing PCIe Gen 7 subsystem
  2. Working with Vendors evaluate IP and make recommendations
  3. Working with Performance Modeling team to analyze SOC/platform Azure IO workloads
  4. Principal PCIe Architect responsible for defining next-generation PCIe/CXL architecture for Microsoft Azure silicon platforms, delivering high-performance, scalable, and reliable I/O subsystems.

Skills

Required

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Nice to have

  • 10+ years of experience in SoC or I/O architecture
  • Deep expertise in PCIe architecture (Gen4/Gen5/Gen6 or later)
  • Understanding of SoC/system architecture and integration
  • Experience delivering PCIe-based subsystems from architecture to silicon production
  • Experience working with cross-functional teams (design, DV, firmware, system software)
  • Experience with PCIe Gen5/Gen6/Gen7 and emerging standards
  • Experience with CXL architecture and memory/coherency models
  • Knowledge of I/O virtualization and system-level interactions (IOMMU, SR-IOV, ATS)
  • Experience with performance modeling/analysis for hyperscale workloads
  • Experience with RAS, power management, and security architecture in I/O subsystems
  • Experience in post-silicon validation, debug, and deployment
  • Proven leadership in driving architecture across multiple programs

What the JD emphasized

  • PCIe Gen 7
  • PCIe/CXL architecture