Principal Hardware Architect

Microsoft Microsoft · Big Tech · Santa Barbara, CA +1 · Quantum Engineering

The Principal Hardware Architect will define the architecture of a next-generation topological quantum system, working across the stack from quantum error correction to fabrication and growth. This role involves evaluating system-level trade-offs and driving key hardware decisions, translating system-level performance goals into subsystem requirements and engineering priorities, and partnering across research, fabrication, and engineering teams.

What you'd actually do

  1. Translate system-level performance goals, including qubit fidelity and error-correction targets, into measurable subsystem requirements and engineering priorities.
  2. Partner across research, fabrication, and engineering teams to evaluate hardware trade-offs and guide architecture decisions across the full hardware stack.
  3. Communicate architectural decisions, assumptions, and trade-offs clearly through documentation and presentations tailored to stakeholders with different technical backgrounds.

Skills

Required

  • Physics
  • Engineering
  • Hardware Architecture
  • System-level trade-offs
  • Subsystem requirements
  • Cross-disciplinary collaboration

Nice to have

  • measurement-based topological quantum computation
  • quantum error correction

What the JD emphasized

  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment.
  • Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment.
  • Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment.
  • 8+ years of experience with measurement-based topological quantum computation.
  • 5+ years of experience in quantum error correction.
  • Demonstrated experience translating system-level performance goals into subsystem requirements, a strong record of driving cross-disciplinary hardware architecture decisions, and the ability to communicate complex technical trade-offs clearly to both specialists and broad engineering audiences.