Principal Memory Controller Architect

Microsoft Microsoft · Big Tech · Raleigh, NC +4 · Silicon Engineering

Seeking a Principal Memory Controller Architect to design and develop next-generation memory controllers for Cobalt CPUs, supporting various DDR technologies and collaborating with cross-functional teams to ensure high performance, efficiency, and reliability of SOCs and IPs.

What you'd actually do

  1. Architecting and development of memory controllers
  2. Reviewing Memory technology roadmaps including, but not limited to: DDR5, DDR6, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM, MRDIMM, LP-MRDIMM, and emerging memory technologies
  3. Working closely with memory controller micro-architects, verification and validation to drive features into production
  4. Working with Vendors evaluate IP and make recommendations
  5. Work with Performance Modeling team to develop cycle approximate model of the controller and also analyze SOC/platform Azure workload results

Skills

Required

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.

Nice to have

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 15+ years technical engineering experience OR equivalent experience.
  • 1+ year(s) experience working on or leading projects from beginning-to-end
  • Delivered Architecture or Design or Verification specs for multiple generations of Memory Controllers
  • Familiar with DDR JEDEC specs
  • Experience in SoC memory hierarchy/architecture, and knowledge of emerging memory technologies.

What the JD emphasized

  • custom silicon
  • memory controller
  • DDR technologies
  • SOC design
  • performance
  • efficiency
  • reliability