Principal Memory Controller Rtl Design Engineer

Microsoft Microsoft · Big Tech · Redmond, WA +4 · Silicon Engineering

This role is for a Principal Memory Controller RTL Design Engineer. The engineer will define and implement micro-architectural specifications, refine implementations for area, power, and performance, integrate functional IP into SoC, and exercise block functionality. Responsibilities also include design quality checks, automating tasks using scripting and AI, collaborating with cross-functional teams, and delivering high-quality functional blocks on schedule. The role requires a Doctorate or Master's/Bachelor's degree with significant experience in Electrical Engineering, Computer Engineering, Computer Science, or related fields. Preferred qualifications include experience with high-performance DDR memory controllers, digital design principles, low power design, Verilog/System Verilog, front-end and synthesis tools, scripting languages, error correction, and industry standard interface protocols. The role involves working with export-controlled information and requires security screening.

What you'd actually do

  1. Define and implement the micro-architectural specification in Verilog or System Verilog
  2. Refine your implementation for area, power and performance
  3. Integration of the functional IP into SoC
  4. Exercise the functionality of the block by writing basic tests
  5. Perform design quality checks such as Lint, CDC/RDC, Low Power Intent, timing QoR

Skills

Required

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Nice to have

  • 10 or more years designing and implementing novel high-performance DDR4 or DDR5 memory controllers
  • Background and understanding of Digital Design principles as part of SoC and/or IP development teams
  • Applied understanding of low power design princiles
  • Highly Proficient in Verilog/System Verilog coding constructs.
  • Highly Proficient in high-speed design principles
  • Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
  • Familiarity with Synthesis and STA tools
  • Ability to write scripts using Perl, Tcl, Python etc.
  • Experience with multi-bit error correction such as Reed-Solomon Encoding
  • Understanding of Industry standard interface protocols such as CHI, APB, AMBA

What the JD emphasized

  • Automate tasks using scripting and AI for efficiency